;buildInfoPackage: chisel3, version: 3.1-SNAPSHOT, scalaVersion: 2.11.11, sbtVersion: 0.13.15, builtAtString: 2017-06-08 17:59:39.314, builtAtMillis: 1496944779314
circuit ALU : 
  module ALU : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip in1 : UInt<32>, flip in2 : UInt<32>, flip alu_opcode : UInt<13>, out : UInt<32>}
    
    clock is invalid
    reset is invalid
    io is invalid
    node mux_alu_opcode = bits(io.alu_opcode, 12, 0) @[ALUTester.scala 34:45]
    node _T_7 = add(io.in1, io.in2) @[ALUTester.scala 38:32]
    node _T_8 = tail(_T_7, 1) @[ALUTester.scala 38:32]
    node _T_9 = sub(io.in1, io.in2) @[ALUTester.scala 39:32]
    node _T_10 = asUInt(_T_9) @[ALUTester.scala 39:32]
    node _T_11 = tail(_T_10, 1) @[ALUTester.scala 39:32]
    node _T_12 = and(io.in1, io.in2) @[ALUTester.scala 40:32]
    node _T_13 = or(io.in1, io.in2) @[ALUTester.scala 41:31]
    node _T_14 = xor(io.in1, io.in2) @[ALUTester.scala 42:32]
    node _T_15 = xor(io.in1, io.in2) @[ALUTester.scala 43:35]
    node _T_16 = not(_T_15) @[ALUTester.scala 43:26]
    node _T_17 = bits(io.in2, 4, 0) @[ALUTester.scala 44:47]
    node _T_18 = dshl(io.in1, _T_17) @[ALUTester.scala 44:38]
    node _T_19 = bits(io.in2, 4, 0) @[ALUTester.scala 45:55]
    node _T_20 = dshr(io.in1, _T_19) @[ALUTester.scala 45:46]
    node _T_21 = asSInt(io.in1) @[ALUTester.scala 48:49]
    node _T_22 = bits(io.in2, 4, 0) @[ALUTester.scala 48:65]
    node _T_23 = dshr(_T_21, _T_22) @[ALUTester.scala 48:56]
    node _T_24 = asUInt(_T_23) @[ALUTester.scala 48:73]
    node _T_25 = asSInt(io.in1) @[ALUTester.scala 49:40]
    node _T_26 = asSInt(io.in2) @[ALUTester.scala 49:56]
    node _T_27 = lt(_T_25, _T_26) @[ALUTester.scala 49:47]
    node _T_28 = lt(io.in1, io.in2) @[ALUTester.scala 50:48]
    node _T_29 = eq(UInt<4>("h0d"), mux_alu_opcode) @[Mux.scala 46:19]
    node _T_30 = mux(_T_29, io.in2, UInt<32>("h0deadf00d")) @[Mux.scala 46:16]
    node _T_31 = eq(UInt<4>("h0c"), mux_alu_opcode) @[Mux.scala 46:19]
    node _T_32 = mux(_T_31, io.in1, _T_30) @[Mux.scala 46:16]
    node _T_33 = eq(UInt<4>("h0b"), mux_alu_opcode) @[Mux.scala 46:19]
    node _T_34 = mux(_T_33, _T_28, _T_32) @[Mux.scala 46:16]
    node _T_35 = eq(UInt<4>("h0a"), mux_alu_opcode) @[Mux.scala 46:19]
    node _T_36 = mux(_T_35, _T_27, _T_34) @[Mux.scala 46:16]
    node _T_37 = eq(UInt<4>("h09"), mux_alu_opcode) @[Mux.scala 46:19]
    node _T_38 = mux(_T_37, _T_24, _T_36) @[Mux.scala 46:16]
    node _T_39 = eq(UInt<4>("h08"), mux_alu_opcode) @[Mux.scala 46:19]
    node _T_40 = mux(_T_39, _T_20, _T_38) @[Mux.scala 46:16]
    node _T_41 = eq(UInt<3>("h07"), mux_alu_opcode) @[Mux.scala 46:19]
    node _T_42 = mux(_T_41, _T_18, _T_40) @[Mux.scala 46:16]
    node _T_43 = eq(UInt<3>("h06"), mux_alu_opcode) @[Mux.scala 46:19]
    node _T_44 = mux(_T_43, _T_16, _T_42) @[Mux.scala 46:16]
    node _T_45 = eq(UInt<3>("h05"), mux_alu_opcode) @[Mux.scala 46:19]
    node _T_46 = mux(_T_45, _T_14, _T_44) @[Mux.scala 46:16]
    node _T_47 = eq(UInt<3>("h04"), mux_alu_opcode) @[Mux.scala 46:19]
    node _T_48 = mux(_T_47, _T_13, _T_46) @[Mux.scala 46:16]
    node _T_49 = eq(UInt<2>("h03"), mux_alu_opcode) @[Mux.scala 46:19]
    node _T_50 = mux(_T_49, _T_12, _T_48) @[Mux.scala 46:16]
    node _T_51 = eq(UInt<2>("h02"), mux_alu_opcode) @[Mux.scala 46:19]
    node _T_52 = mux(_T_51, _T_11, _T_50) @[Mux.scala 46:16]
    node _T_53 = eq(UInt<1>("h01"), mux_alu_opcode) @[Mux.scala 46:19]
    node _T_54 = mux(_T_53, _T_8, _T_52) @[Mux.scala 46:16]
    io.out <= _T_54 @[ALUTester.scala 36:10]
    when UInt<1>("h01") : @[ALUTester.scala 56:16]
      node _T_57 = eq(reset, UInt<1>("h00")) @[ALUTester.scala 57:11]
      when _T_57 : @[ALUTester.scala 57:11]
        printf(clock, UInt<1>(1), "io.alu_opcode = %d mux_alu_opcode = %d io.in1 = %x io.in2 = %x io.out = %x\n", io.alu_opcode, mux_alu_opcode, io.in1, io.in2, io.out) @[ALUTester.scala 57:11]
        skip @[ALUTester.scala 57:11]
      skip @[ALUTester.scala 56:16]
    
